Master10
Computer & Digital Awareness Module

Hardware Architecture, CPU & Memory Hierarchy

Computer hardware architecture is organized around the classical Von Neumann model, comprising the Central Processing Unit (CPU), primary memory, input/output peripherals, and secondary storage. The CPU executes instructions via the fetch-decode-execute cycle using the Arithmetic Logic Unit (ALU), Control Unit (CU), and high-speed internal registers. The memory hierarchy balances access speed, cost, and storage capacity: ultra-fast CPU registers and SRAM-based cache memory sit at the apex, followed by volatile primary RAM (DRAM), non-volatile ROM, and secondary storage like Solid State Drives (SSDs). Understanding byte storage scales (KB to TB) and bus interfaces is essential for computing literacy.

Key Concepts & Examination Highlights

  • The Von Neumann architecture, proposed in 1945 by mathematician John von Neumann, stores both program instructions and data in the same shared physical memory.
  • The CPU contains three primary functional units: the Arithmetic Logic Unit (ALU) for mathematical/logical computations, the Control Unit (CU) for sequencing, and Registers for high-speed temporary storage.
  • Cache memory, constructed using fast Static RAM (SRAM), bridges the speed disparity between the fast CPU and the slower Dynamic RAM (DRAM) main memory.
  • Data storage measurement units scale by powers of 2 in binary computing: 1 Byte = 8 bits, 1 Kilobyte (KB) = 1,024 Bytes, 1 Megabyte (MB) = 1,024 KB, and 1 Gigabyte (GB) = 1,024 MB.
  • Static RAM (SRAM) uses flip-flops made of 4 to 6 transistors per bit and does not require periodic refreshing, making it faster and suitable for CPU caches.
  • Dynamic RAM (DRAM) stores each bit of data in a tiny capacitor paired with a transistor, requiring periodic electrical refreshing to retain data, and forms main computer memory.
  • The Arithmetic Logic Unit (ALU) performs all arithmetic calculations (addition, subtraction) and logical operations (AND, OR, NOT), while the Control Unit (CU) directs the flow of instructions and data.
  • The system bus connects CPU, memory, and I/O devices, consisting of three separate buses: Data Bus (bidirectional), Address Bus (unidirectional from CPU), and Control Bus.
  • Moore's Law, formulated by Intel co-founder Gordon Moore in 1965, observed that the number of transistors on a microchip doubles roughly every two years with minimal cost increase.
  • Pipelining is a CPU implementation technique where multiple instructions are overlapped in execution across different hardware stages to increase instruction throughput.
  • Flash memory is a non-volatile solid-state storage technology utilizing floating-gate transistors, forming the basis of Solid State Drives (SSDs), USB drives, and SD cards.
  • The Harvard architecture separates physical storage and signal pathways for instructions and data, allowing simultaneous memory access, unlike the shared-bus Von Neumann architecture.
  • The CPU instruction cycle consists of four sequential phases: Fetch (retrieve instruction from memory), Decode (interpret opcode), Execute (perform operation), and Writeback (store results).
  • The Program Counter (PC) register stores the memory address of the next instruction to be fetched and executed by the CPU.
  • The Instruction Register (IR) holds the current instruction while it is being decoded and executed by the Control Unit.
  • Cache memory operates in a hierarchy: Level 1 (L1) cache is the fastest and smallest, located directly inside the CPU core; L2 is larger and slightly slower; and L3 is shared across multiple CPU cores.
  • The Memory Management Unit (MMU) is a hardware component in the CPU that translates virtual memory addresses into physical RAM addresses using page tables and the Translation Lookaside Buffer (TLB).
  • Direct Memory Access (DMA) allows hardware subsystems (such as disk controllers and network cards) to transfer data directly to and from main RAM without continuously burdening the CPU.
  • Non-Volatile Memory Express (NVMe) is a host controller interface and storage protocol designed to accelerate data transfer across PCI Express (PCIe) buses for high-speed solid-state drives.
  • RISC (Reduced Instruction Set Computer) utilizes simple, fixed-length instructions executed in a single clock cycle, exemplified by ARM and RISC-V architectures.
  • CISC (Complex Instruction Set Computer) incorporates a broad set of complex, variable-length instructions capable of multi-step operations, exemplified by Intel and AMD x86 architectures.
  • Clock speed, measured in gigahertz (GHz), indicates the number of electrical clock cycles a CPU executes per second, though IPC (Instructions Per Cycle) determines overall throughput.
  • Read-Only Memory (ROM) is non-volatile memory that retains firmware instructions permanently, existing in forms such as PROM (Programmable), EPROM (Erasable by UV light), and EEPROM (Electrically Erasable).
  • The Basic Input/Output System (BIOS) and Unified Extensible Firmware Interface (UEFI) are non-volatile firmware programs stored on motherboard EEPROM to initialize hardware during the Power-On Self-Test (POST).
  • Graphics Processing Units (GPUs) contain thousands of smaller, highly efficient arithmetic cores designed for massive parallel processing of matrix and vector data.
  • The control unit (CU) of a CPU decodes binary opcodes into micro-operations and generates synchronized electronic timing control signals across internal buses.
  • The Arithmetic Logic Unit (ALU) contains adders, subtractors, bitwise logic gates (AND, OR, XOR, NOT), and bit-shift circuits to perform integer arithmetic and logic.
  • Registers are the fastest and smallest memory storage locations inside the CPU, including general-purpose registers (AX, BX, CX, DX) and special-purpose registers (PC, SP, IR).
  • The Stack Pointer (SP) register holds the memory address of the current top element of the call stack in RAM, managing function call frames, local variables, and return addresses.
  • The Status Register (Flags Register) contains single-bit conditional condition codes (such as Zero Flag, Carry Flag, Overflow Flag, Sign Flag) updated after ALU operations.
  • The system clock generator produces steady square-wave electrical pulses at fixed frequencies that synchronize all synchronous internal operations of the CPU and motherboard.
  • Instruction pipelining divides instruction execution into multiple distinct hardware stages (such as 5-stage classic RISC: IF, ID, EX, MEM, WB), increasing instruction execution throughput.
  • Pipeline hazards in superscalar CPUs are categorized into Structural hazards (hardware resource conflicts), Data hazards (data dependencies), and Control hazards (branch jumps).
  • Branch prediction algorithms (static and dynamic branch predictors) predict the outcome of conditional branch instructions to avoid costly pipeline flush stalls.
  • Out-of-Order (OoO) execution dynamically schedules instructions to execute as soon as their operand data is available rather than following strict sequential program order.
  • Superscalar processors feature multiple parallel execution units (multiple ALUs and FPUs) capable of executing more than one instruction per clock cycle (IPC>1IPC > 1).
  • Simultaneous Multithreading (SMT), commercialized as Intel Hyper-Threading, allows a single physical CPU core to appear as multiple logical processors to the operating system.
  • Virtual memory uses paged physical memory allocations and secondary storage swap space to provide each executing process with a large, isolated contiguous address space.
  • The Translation Lookaside Buffer (TLB) is a high-speed associative hardware cache in the MMU that stores recent virtual-to-physical memory page address translations.
  • A page fault occurs when an executing program accesses a virtual memory page that is currently not mapped into physical RAM, requiring the operating system to load it from disk.
  • Dynamic RAM (DRAM) cells must be periodically refreshed every few milliseconds (typically 64 ms) because the electric charge stored in the memory capacitor gradually leaks away.
  • Synchronous DRAM (SDRAM) synchronizes its data transfer interface with the system bus clock, evolving across generations into DDR, DDR2, DDR3, DDR4, and DDR5.
  • Double Data Rate (DDR) SDRAM transfers data on both the rising edge and falling edge of the clock signal, doubling data throughput without increasing clock frequency.
  • Error-Correcting Code (ECC) memory contains parity bits and Hamming code logic capable of detecting and correcting single-bit memory errors in mission-critical servers.
  • The PCI Express (PCIe) bus is a high-speed serial computer expansion bus standard that uses point-to-point lane topologies (×1,×4,×8,×16\times 1, \times 4, \times 8, \times 16) to connect graphics cards and SSDs.
  • Solid State Drives (SSDs) utilize NAND flash memory organized into blocks and pages, requiring block-level erasing before individual pages can be reprogrammed.
  • Wear leveling algorithms in SSD controllers distribute write and erase cycles uniformly across all NAND flash blocks to maximize drive endurance and lifespan.
  • The TRIM command informs an SSD controller which data blocks are no longer in use, allowing the drive to perform background garbage collection and maintain write speeds.
  • Universal Serial Bus (USB) standards have evolved from USB 1.1 (12 Mbps) and USB 2.0 (480 Mbps) to USB 3.0 (5 Gbps), USB 3.2 (20 Gbps), and USB4 (up to 80 Gbps via USB Type-C).
  • Thunderbolt is an advanced hardware interface developed by Intel and Apple that multiplexes PCIe, DisplayPort, and DC power over high-speed USB-C cables at up to 40–80 Gbps.
Curriculum & Reference Sources: IEEE Computer Society, ACM Computing Curricula, and standard computer organization references (Patterson & Hennessy).

Sample Solved Questions & Concept Explanations

8 Verified Concept Questions
Q1.EASY

Which computer component is known as volatile memory because its stored data is lost when the power supply is turned off?

Q2.EASY

Which component inside a Central Processing Unit (CPU) is specifically responsible for carrying out arithmetic computations and logical comparison operations?

Q3.EASY

Which type of ultra-fast memory is positioned directly between the CPU registers and main RAM to temporarily hold frequently accessed data and instructions?

Q4.EASY

Why does Dynamic RAM (DRAM) require periodic electrical refreshing thousands of times per second, unlike Static RAM (SRAM)?

Q5.EASY

What type of non-volatile semiconductor memory can be repeatedly erased and reprogrammed using pulsed electrical voltages without requiring ultraviolet light exposure?

Q6.EASY

In CPU architecture, which dedicated processor register holds the memory address of the next sequential instruction to be fetched and executed?

Q7.EASY

Which unit of measurement is standardly used to express the clock frequency and operational cycle speed of modern computer microprocessors?

Q8.EASY

Which major internal communication pathway connects the CPU, memory, and peripheral controllers across a computer motherboard?